VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications

[[abstract]]The paper presents a low memory and high speed VLSI architecture for 2D lifting-based lossless 5/3 filter discrete wavelet transform (DWT). The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity, transforming signal with extension, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operation of JPEG2000 and MPEG-4 applications. Basing on the proposed architecture, we designed and simulated a 2D DWT VLSI chip by 0.35 弮m 1P4M CMOS technology. The memory requirement of the N?N 2D DWT is N, and it can operate at 100 MHz clock frequency.[[notice]]需補會議日期、性質、主辦單位[[conferencetype]]國際[[conferencedate]]20050523~2005052

An efficient object recognition and self-localization system for humanoid soccer robot

[[abstract]]In the RoboCup soccer humanoid league competition, the vision system is used to collect various environment information as the terminal data to finish the functions of object recognition, coordinate establishment, robot localization, robot tactic, barrier avoiding, etc. Thus, a real-time object recognition and high accurate self-localization system of the soccer robot becomes the key technology to improve the performance. In this work we proposed an efficient object recognition and self-localization system for the RoboCup soccer humanoid league rules of the 2009 competition. We proposed two methods : 1) In the object recognition part, the real-time vision-based method is based on the adaptive resolution method (ARM). It can select the most proper resolution for different situations in the competition. ARM can reduce the noises interference and make the object recognition system more robust as well. 2) In the self-localization part, we proposed a new approach, adaptive vision-based self-localization system (AVBSLS), which uses the trigonometric function to find the coarse location of the robot and further adopts the measuring artificial neural network technique to adjust the humanoid robot position adaptively. The experimental results indicate that the proposed system is not easily affected by the light illumination. The object recognition accuracy rate is more than 93% on average and the average frame rate can reach 32 fps (frame per second). It does not only maintain the higher recognition accuracy rate for the high resolution frames, but also increase the average frame rate for about 11 fps compared to the conventional high resolution approach and the average accuracy ratio of the localization is 92.3%.[[notice]]需補會議地點、主辦單位[[conferencetype]]國際[[conferencedate]]20100818~2010082

A new video object segmentation algorithm using the morphological technique

[[abstract]]In this paper, we propose a new video object segmentation algorithm using the morphological technique. Several video object segmentation algorithms use mathematical morphology to generate the object masks, however the operations of the mathematical morphology have two drawbacks: (1) high computation complexity and (2) the quality of the object masks depends on the chosen morphological structuring element. There are many techniques to speed up the morphological operations by hardware implementation, but without discussions about reducing the influence of the choice of the structuring elements. By adding a pre-processing mechanism, the proposed algorithm effectively reduce the influences of the chosen structuring elements based on continuity of shape features and times of morphological operations. Experimental results show that our algorithm can improve the speed of filling operations of the object masks and accuracy of segmentation.[[notice]]需補會議地點、主辦單位[[conferencetype]]國際[[conferencedate]]20080731~2008080

Stereo vision-based self-localization system for RoboCup

[[abstract]]This work proposes a new Stereo Vision-Based Self-Localization System (SVBSLS) for the RoboCup soccer humanoid league rules for the 2010 competition. The humanoid robot integrates the information from the pan/tilt motors and stereo vision to accomplish the self-localization and measure the distance of the robot and the soccer ball. The proposed approach uses the trigonometric function to find the coarse distances from the robot to the landmark and the robot to the soccer ball, and then it further adopts the artificial neural network technique to increase the precision of the distance. The statistics approach is also used to calculate the relationship between the humanoid robot and the position of the landmark for self-localization. The experimental results indicate that the localization system of SVBSLS in this research work has 100% average accuracy ratio for localization. The average error of distance from the humanoid soccer robot to the soccer ball is only 0.64 cm.[[notice]]需補會議日期、性質、主辦單位[[conferencedate]]20110627~2011063

New architecture for high throughput-rate real-time 2-D DCT and the VLSI design

[[abstract]]The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PLA) to replace multipliers, (2) overlapped row-column operations and pipeline structure to reduce the total computation time, and (3) highly modular and regular structure for the efficient VLSI implementation. The architecture is implemented to a 8×8 2-D DCT. The circuit is designed by UMC's 0.8 μm spdm CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplication and accumulations per second[[conferencetype]]國際[[conferencedate]]19960923~19960927[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Rochester, NY, US

Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform for JPEG2000

Non

High efficiency architecture of ESCOT with pass concurrent context modeling scheme for scalable video coding

[[abstract]]In this work, we propose a high efficiency hardware architecture of embedded sub-band coding with optimal truncation (ESCOT) with pass concurrent context modeling (PCCM) scheme for wavelet-based scalable video coding (SVC). PCCM can merge the three-pass process of bit-plane coding into a single pass process. It improves the efficiency of the ESCOT algorithm and reduces the frequencies of memory access, which can reduce the power consumption. Furthermore we use the parallel architecture scheme of PCCM to encode 4 samples concurrently, which improves the operation speed and can reduce 40% of internal memory requirement. We use Artison TSMC 0.18 mum 1P6M standard cell library to design and implement the proposed concurrent context modeling. The simulation results indicate that PCCM can have an operation speedup of 9.5 compared to the standard context modeling of ESCOT, and it can operate for 1080 p with frame rate of 30 fps at clock rate of 125 MHz.[[conferencetype]]國際[[conferencedate]]20080518~20080521[[iscallforpapers]]Y[[conferencelocation]]Seattle, WA, US

The design of a delta-sigma modulator with low clock feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors

[[abstract]]The performance of a delta-sigma modulator (Δ ΣM) is degraded due to the low op-amp gain, the clock feedthrough noise, and the right or fault of charge transferring between capacitors. Hurst et al. in 1993 suggested an architecture which uses reduced sensitivity to the op-amp gain. Since the low op-amp gain is much easier to design and makes the design of a Δ ΣM become very easy. However, they do not overcome the noise effect of the Δ ΣM. Here, another design is proposed and the effect of noise is reduced[[conferencetype]]國際[[conferencedate]]19970609~19970612[[conferencelocation]]Hong Kon

High density QR code with multi-view scheme

[[abstract]]Since the data storage capacity per unit area of a QR code is very limited, it is restricted in various QR code applications. An approach is proposed based on visual skew to improve the data capacity of the QR code. The proposed method can enhance the capacity of the QR code per unit area by using different angle views to combine several QR codes together. The storage capacity of the proposed mechanism can be increased 1.5 times per unit area more than that of the normal QR code.[[notice]]補正完畢[[incitationindex]]SCI[[booktype]]紙

High-speed EBCOT with dual context-modeling coding architecture for JPEG2000

[[abstract]]This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. The tier-1 of the EBCOT consumes most of the computation time in a JPEG2000 encoding system, and the proposed parallel architecture can increase the throughput rate of the context-modeling. To match the high throughput rate of the parallel context-modeling architecture, and efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 185MHz to encode one symbol each cycle. Compared with the conventional context-modeling architecture, our parallel architecture can decrease the execution time about 25%.[[conferencetype]]國際[[conferencedate]]20040523~20040526[[conferencelocation]]溫哥華, 加拿